(PKG of 10) HEF4014BP 8-Bit Static Shift Register, CD4014, PDIP-16, Philips
Package of 10!
New old stock (NOS), unused, genuine part: Philips HEF4014BP
Manufacturer: Philips
Manufacturer Part Number: HEF4014BP
Product Category: Logic ICs, Shift Registers
Logic Family: CD4000 (CD4014)
Package / Case: PDIP-16, Plastic
RoHS: NO
Packaging: Anti-Static
DESCRIPTION
The HEF4014B is a fully synchronous edge-triggered 8-bit static shift register with eight synchronous parallel inputs (P0 to P7), a synchronous serial data input (DS), a synchronous parallel enable input (PE), a LOW to HIGH edge-triggered clock input (CP) and buffered parallel outputs from the last three stages (O5 to O7).
Operation is synchronous and the device is edge-triggered on the LOW to HIGH transition of CP. Each register stage is of a D-type master-slave flip-flop. When PE is HIGH, data is loaded into the register from P0 to P7 on the LOW to HIGH transition of CP. When PE is LOW, data is shifted to the first position from DS, and all the data in the register is shifted one position to the right on the LOW to HIGH transition of CP. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times
Description
Package of 10!
New old stock (NOS), unused, genuine part: Philips HEF4014BP
Manufacturer: Philips
Manufacturer Part Number: HEF4014BP
Product Category: Logic ICs, Shift Registers
Logic Family: CD4000 (CD4014)
Package / Case: PDIP-16, Plastic
RoHS: NO
Packaging: Anti-Static
DESCRIPTION
The HEF4014B is a fully synchronous edge-triggered 8-bit static shift register with eight synchronous parallel inputs (P0 to P7), a synchronous serial data input (DS), a synchronous parallel enable input (PE), a LOW to HIGH edge-triggered clock input (CP) and buffered parallel outputs from the last three stages (O5 to O7).
Operation is synchronous and the device is edge-triggered on the LOW to HIGH transition of CP. Each register stage is of a D-type master-slave flip-flop. When PE is HIGH, data is loaded into the register from P0 to P7 on the LOW to HIGH transition of CP. When PE is LOW, data is shifted to the first position from DS, and all the data in the register is shifted one position to the right on the LOW to HIGH transition of CP. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times
Reviews (0)
Be the first to write a review