
(PKG of 5) SN74H108N Dual J-K Negative-Edge-Triggered Flip-Flops, PDIP-14, TI
Package of 5!
New old stock (NOS), unused, genuine part: Texas Instruments SN74H108N Dual J-K Negative-Edge-Triggered Flip-Flops with Preset, Common Clear, and Common Clock, PDIP-14
Manufacturer: Texas Instruments
Manufacturer Part Number: SN74H108N
74 Series Part: 74H108
Product Category: Logic ICs, Flip Flops
Product: J-K Type Flip-Flop
Logic Family: H
Number of Circuits: 2
Supply Voltage - Min: 4.75 V
Supply Voltage - Max: 5.25 V
Package / Case: PDIP-14, Plastic
RoHS: NO
Packaging: Anti-Static
DESCRIPTION
These dual monolithic J-K flip-flops are negative-edge-triggered. They feature individual J, K, and asynchronous preset inputs to each flip-flop as well as common clock and asynchronous clear inputs. When the clock goes high, the inputs are enabled and data will be accepted. Logical state of J and K inputs may be allowed to change when the clock pulse is in a high state and bistable will perform according to the truth table as long as minimum set-up times are observed. Input data is transferred to the outputs on the negative edge of the clock pulse.
Note: Date code may differ from picture. Part Number and Manufacturer are identical to what is shown.
Description
Package of 5!
New old stock (NOS), unused, genuine part: Texas Instruments SN74H108N Dual J-K Negative-Edge-Triggered Flip-Flops with Preset, Common Clear, and Common Clock, PDIP-14
Manufacturer: Texas Instruments
Manufacturer Part Number: SN74H108N
74 Series Part: 74H108
Product Category: Logic ICs, Flip Flops
Product: J-K Type Flip-Flop
Logic Family: H
Number of Circuits: 2
Supply Voltage - Min: 4.75 V
Supply Voltage - Max: 5.25 V
Package / Case: PDIP-14, Plastic
RoHS: NO
Packaging: Anti-Static
DESCRIPTION
These dual monolithic J-K flip-flops are negative-edge-triggered. They feature individual J, K, and asynchronous preset inputs to each flip-flop as well as common clock and asynchronous clear inputs. When the clock goes high, the inputs are enabled and data will be accepted. Logical state of J and K inputs may be allowed to change when the clock pulse is in a high state and bistable will perform according to the truth table as long as minimum set-up times are observed. Input data is transferred to the outputs on the negative edge of the clock pulse.
Note: Date code may differ from picture. Part Number and Manufacturer are identical to what is shown.
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